1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device that includes redundant word lines for replacing defective word lines and redundant bit lines for replacing defective bit lines.
2. Description of Related Art
A semiconductor memory device represented by a DRAM (Dynamic Random Access Memory) includes so many memory cells that there is no avoiding including some defective memory cells. Accordingly, redundant word lines and redundant bit lines are prepared in advance in a memory cell array. When a defective memory cell is detected in an operation test, one of the redundant word lines replaces a defective word line corresponding to the defective memory cell or one of the redundant bit lines replaces a defective bit line corresponding to the defective memory cell, thereby repairing the memory device (see Japanese Patent Applications Laid-open Nos. 2010-198694, 2009-211796, 2004-133970, and 2004-63023).
Generally, a row fuse circuit that has addresses of defective word lines stored therein is arranged near a row decoder, and a column fuse circuit that has addresses of defective bit lines stored therein is arranged near a column decoder. This achieves the shortest signal lines that connect the row fuse circuit to the row decoder and those that connect the column fuse circuit to the column decoder. Therefore, it is possible to minimize an access delay.
However, the conventional techniques have the following problems. In the above layout, the row fuse circuit has an extension direction differing by 90° from that of the column fuse circuit, which causes the time required for trimming of fuse elements (address programming by laser irradiation) to be long. Furthermore, because it is impossible to efficiently arrange the fuse elements, the occupation area of the row fuse circuit and the column fuse circuit on a chip increases.